specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 53012hk 20120516-s00003 no.a2063-1/9 LC72725KMA overview the LC72725KMA is ic that implement the signal processing required by the european broadcasting union rds (radio data system) standard and by the us nrsc (na tional radio system committee) rbds (radio broadcast data system) standard. this ic include band-pass filter, demodulato r, and data buffer on chip. rds data can be read out from this on-chip memory by external clock input in slave operation mode. functions ? bandpass filter: switche d capacitor filter (scf) ? rds demodulation: 57khz carrier and rds data cloc k regeneration, biphase decode, differential decode. ? buffer: 128 bit (about 100ms) can be restored in the on-chip data buffer ram. ? data output: master or slave output mode can be selected. ? rds-id: detect rds signal which can be reset by rst signal input. ? standby control: crystal oscillator can be stopped. ? fully adjustment free ? low voltage specifications absolute maximum ratings at ta = 25 ? c, v ss d = v ss a = 0v parameter symbol pin name conditions ratings unit maximum supply voltage v dd max v dd d, v dd a * v dd a ? v dd d+0.3v -0.3 to +6.5 v maximum input voltage v in 1 max test, mode, xin, rdcl, rst -0.3 to v dd d+0.3 v v in 2 max mpxin, cin -0.3 to v dd a+0.3 v maximum output voltage v o 1 max rds-id(ready) -0.3 to +6.5 v v o 2 max xout, rdda, rdcl -0.3 to v dd d+0.3 v v o 3 max flout -0.3 to v dd a+0.3 v maximum output current i o 1 max xout, flout, rdda, rdcl +2.0 ma i o 2 max rds-id(ready) +8.0 ma * v dd a ? v dd d+0.3v continued on next page. ordering number : ena2063 cmos ic rds(rbds) demodulation ic
LC72725KMA no.a2063-2/9 continued from preceding page. parameter symbol pin name conditions ratings unit allowable power dissipation pd max ta ? 85 ? c 140 mw operating temperature topr1 v dd = 2.7v to 5.5v -20 to +70 ? c topr2 v dd = 3.0v to 5.5v -40 to +85 ? c storage temperature tstg -40 to +125 ? c allowable operating ranges at ta = -20 to +70 ? c, v ss d = v ss a = 0v, v dd d = v dd a = 2.7v to 5.5v ta = -40 to +85 ? c, v ss d = v ss a = 0v, v dd d = v dd a = 3.0v to 5.5v parameter symbol pin name conditions ratings unit min typ max supply voltage v dd 1 v dd d, v dd a ta = -20 to +70 ? c 2.7 5.5 v v dd 2 v dd d, v dd a ta = -40 to +85 ? c 3.0 5.5 input high-level voltage v ih 1 test, mode, rst 0.7v dd d 6.5v v ih 2 rdcl 0.7v dd d v dd dv input low-level voltage v il test, mode, rst, rdcl 0 0.3v dd dv output voltage v o 1 rdda, rdcl v dd dv v o 2 rds-id(ready) 6.5 v input amplitude v in mpxin f = 57 ? 2khz 1.6 50 mvrms vxin xin 400 1500 mvrms guaranteed crystal oscillator frequencies xtal xin, xout ci ? 120 ? 4.332 mhz crystal oscillator operating range txtal xin, xout fo = 4.332mhz ? 100 ppm rdcl setup time tcs rdcl, rdda 0 ? s rdcl high-level time tch rdcl 0.75 ? s rdcl low-level time tcl rdcl 0.75 ? s data output time tdc rdcl, rdda 0.75 ? s ready output time trc rdcl, ready 0.75 ? s ready low-level time trl ready 107 ms
LC72725KMA no.a2063-3/9 electrical characteristics for the allowable operating ranges parameter symbol pin name conditions ratings unit min typ max input resistance rmpxin mpxin-v ss a f = 57khz 100 k ? rcin cin-v ss a f = 57khz 100 k ? internal feedback resistance rf xin 1.0 m ? center frequency fc flout 56.5 57.0 57.5 khz -3db band width bw-3db flout 2.5 3.0 3.5 khz gain gain mpxin-flout f = 57khz 28 31 34 db stop band attenuation att1 flout ? f = ? 7khz 30 db att2 flout f<45khz, f>70khz 40 db att3 flout f<20khz 50 db reference voltage output vref vref v dd a = 3v 1.5 v hysteresis vhis test, mode, rst, rdcl 0.1v dd d v output low-level voltage v ol 1 rdda, rdcl i = 2ma 0.4 v v ol 2 rds-id(ready) i = 8ma 0.4 v output high-level voltage v oh rdda, rdcl i = 2ma v dd d-0.4 v input high-level current i ih 1 test, mode, rst, rdcl v i = 6.5v 5.0 ? a i ih 2 xin v i = v dd d 2.0 11 ? a input low-level current i il 1 test, mode, rst, rdcl v i = 0v 5.0 ? a i il 2 xin v i = 0v 2.0 11 ? a output off leakage current ioff rds-id(ready) v o = 6.5v 5.0 ? a current drain i dd v dd d+v dd a v dd d+v dd a (v dd d = v dd a = 3v) 5 ma package dimensions unit:mm (typ) 3431 sanyo : soic16 9.9 3.9 6.0 1 16 0.2 0.825 0.42 1.27 0.175 1.75 max
LC72725KMA no.a2063-4/9 pin assignment block diagram reference voltage cin flout vref vref antialiasing filter 57khz bpf (scf) smoothing filter mpxin +3v v dd a v ss a pll (57khz) clock recovery (1187.5hz) +3v v dd d rds-id/ ready rst v ss d data decoder xout xin test test clk(4.332mhz) osc ram (128bit) rdda rdcl rds-id detect mode LC72725KMA top view 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 xout test cin flout v ss a v dd a mpxin vref rds-id/ready rdcl rdda rst mode v dd d xin v ss d
LC72725KMA no.a2063-5/9 pin descriptions pin no. pin name i/o function pin circuit 3 vref output reference voltage output (vdda/2) 4 mpxin input baseband (multiplexed) signal input 7 flout output subcarrier output (filter output) 8 cin input subcarrier input (comparator input) 5 v dd a - analog system power supply (+3v) 6 v ss a - analog system ground 14 xout output crystal oscillator output (4.332mhz) 13 xin input crystal oscillator input (external reference signal input) 9 test test input 10 mode read out mode (0:master, 1:slave) 15 rst rds-id/ram reset (active high) 2 rdda output rds data output 16 rdcl i/o rds clock output (master mode) / rds read out clock input (slave mode) 1 rds-id/ ready output rds reliability data output (high:data with high rds reliability low: data with low rds reliability) ready output (active high) 12 v dd d - digital system power supply (+3v) 11 v ss d - digital system ground v dd a v ss a v dd d v ss d v dd a vref v ss a v dd d xout xin v ss d s v ss d v ss d v dd d v ss d s v ss d v dd d
LC72725KMA no.a2063-6/9 input/output data format test mode circuit operation mode rdcl pin rds-id/ready pin 0 0 master read out mode cl ock output rds-id output 0 1 slave read out mode clock input ready output 1 0 standby mode (crystal oscillator stopped) - - 1 1 ic test mode which is not available to user applications. - - rst pin rst = 0 normal operation rst = 1 rds-id ? demodulation circuit clear + ready ? memory clear (when slave mode) rds-id/ready pin master mode rds-id output (active-high) slave mode ready output (active-high) note: rds-id(ready) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data. rdcl/rdda output timi ng in master mode rds-id output timing note: rds-id is high: data with high rds reliability, low: data with low rds reliability 421 ? ? ? ?
LC72725KMA no.a2063-7/9 rst operation in master mode note: rdcl and rdda outputs keep high level after input of rst until rds detection circuit output is detected. rdcl operation in slave mode parameter symbol pin name conditions ratings unit min typ max rdcl setup time tcs rdcl,rdda 0 ? s rdcl high-level time tch rdcl 0.75 ? s rdcl low-level time tcl rdcl 0.75 ? s data output time tdc rdcl,rdda 0.75 ? s ready output time trc rdcl,ready 0.75 ? s ready high-level time trh ready 107 ms ? rdcl rdda rdsdetection circuit output (ic internal) rst tp3 ? 250ns ? ? ? ? ? ?
LC72725KMA no.a2063-8/9 notes: 1. rdcl input must be started after ready signal goes high. when ready signal is low, rdcl must be low level. 2. ready status must be checked after trc time from rdcl is set low. if the ready status is high, then next read cycle can be continued. if the ready status is low, next rdcl clock input must be stopped. 3. if the above condition is satisfied, rds data (rdda) ca n be read out at both rising and falling edge of rdcl. 4. ready signal goes low after the last data is read out from on-chip memory. if one rds data is stored in the memory, ready signal goes high again. 5. when the reception channel is changed, a memory an d ready reset must be applied using rst input. if a reset is not applied, reception data from the previous channel may remain in memory. if rst input is applied, reception data is not stored in memo ry until the first rds-id is detected , and ready output goes high after the first rds-id is det ected. after the first rds-id is detected, reception data is st ored even if rds-id is not detected. 6. the readout mode may be switched between master and slave modes during readout. applications must observe the following points to assure data continuity during this operation. 1) data acquisition timing in master made data must be read on the falling edge of rdcl 2) timing of the switch from master mode to slave mode after the rdcl output goes low and the rdda data has been acquired, the application must set mode high immediately. then, the microcontroller starts output by setting the rdcl signal low. the microcontroller rdcl output must start within 840 ? s (tms) after rdcl went low. in this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. 3) timing of the switch from slave mode to master mode after all data has been read from memory and ready has gone high, the application must then wait until ready goes low once again the next time (timing a in the figure), immediately read out one bit of data and input the rdcl clock. then, at the point ready goes high, the microcontr oller must terminate rdcl output and then set mode low. the application must switch mode to low within 840 ? s (tms) after ready goes low (timing a in the figure). n n+1 n-1 n-2 m m+1 m+2 timing a t ms t sm input output input output input output rdcl (microcontroller status) rdcl (ic status) rdcl mode read y rdd a undefined ? ? ? ? ? ? ? ? ?
LC72725KMA no.a2063-9/9 sample application connection circ uit (for master mode operation) note: if the rst pin is unused, it must be connected to ground. ps xout test v ss d 1 2 16 15 14 rdcl rst 13 9 xin mode rst rdcl rdsid/ready 4.332mhz v ss d 22pf v ss d 22pf cin flout v ss a v ss a v dd a v dd a 8 7 6 5 4 + 3 10 ? ? f 330pf vref v ss d v dd d 12 11 v ss d 0.1 ? ? rdsid/ready rdda rdda 10 this catalog provides information as of may, 2 012. specifications and info rmation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
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